ADA4255ACPZ-R7 datasheet(39/64 Pages) AD

39 / 64 page

Data Sheet

ADA4255

APPLICATIONS INFORMATION

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Rev. 0 | 39 of 64

INPUT AND OUTPUT OFFSET VOLTAGE AND

NOISE

The offset voltage of the ADA4255 has two main components: the

input offset voltage due to the input amplifiers and the output offset

due to the output amplifier. The total offset voltage RTI is found

by dividing the output offset by the programmed gain and adding

this value to the input offset voltage. At high gains, the input offset

voltage dominates, whereas at low gains, the output offset voltage

dominates. The total offset voltage is

Total Input Offset Voltage (RTI) =VOSI + (VOSO/GAIN)

Total Output Offset Voltage (Referred to Output (RTO)) =VOSI ×

Gain + VOSO

The preceding equations can also be used to calculate the offset

drift in a similar manner.

The noise of the ADA4255 behaves similarly to the voltage offset.

There are two components: the input voltage noise due to the input

amplifiers and the output voltage noise due to the output amplifiers.

The total noise RTI is found by dividing the output voltage noise by

the programmed gain and root-sum-squaring with the input voltage

noise. At high gains the input voltage noise dominates, whereas

at low gains the output voltage noise dominates. The total voltage

noise is

Total Input Voltage Noise RTI

= eni2+ enoGain 2

(4)

Total Output Voltage Noise RTO

= eni×Gain2+ eno2

(5)

ADC CLOCK SYNCHRONIZATION

The ADA4255 incorporates several clock synchronization features

that allow the internal clock to be synchronized with other circuitry,

such as an ADC. Synchronizing the system filters residual ripple

due to the internal chopping of the ADA4255. When using these

synchronization features, GPIO4 is configured to accept an external

clock signal or output one of the internal clock signals.

When an external clock is provided to the ADA4255, an on-chip

clock divider is configured via the SYNC bits (Register SYNC_CFG)

to achieve a nominal 1 MHz clock. The 1 MHz clock is further

divided by 8 to 125 kHz and controls the device chopping. The

chopping clock edges can be configured to coincide with either

the rising or falling edges of the provided clock via SYNC_POL

bit (Register SYNC_CFG). This configuration is recommended for

ADC synchronization. The ADA4255, when configured to accept an

external clock, requires that this clock always be active and have a

duty cycle of 50% to maintain charge pump operation.

Alternatively, the internal clock can be output to GPIO4 so that

other circuits can use it. Either 1 MHz or 125 kHz can be selected

via the CLK_OUT_SEL bit (Register SYNC_CFG).

When the ADA4255 is driving the AD4007 1 MSPS successive

approximation register (SAR) ADC as shown in Figure 105, the rec-

ommended configuration is to provide the 50% duty cycle convert

signal to the ADA4255 as a clock input. In this case, SYNC is set to

0b000 because the CNV period is 1 μs. Set the SYNC_POL bit to

1 to synchronize the chopping clock to the rising edge of the CNV

signal. When configured in this way, the output of the ADA4255 has

the maximum time to settle after a chopping edge, and chopping

edges do not occur during the ADC conversion phase. It is recom-

mended to enable the high-Z mode of the AD4007 to maximize

system performance.

When the ADA4255 is driving the AD7768 Σ-Δ ADC as shown

in Figure 106, the recommended configuration is to provide the

internal 32 MHz clock of the AD7768 to the ADA4255 as a clock

input. In this case, SYNC is set to 0b101 to divide 32 MHz down

to 1 MHz for the ADA4255. The SYNC setting has no impact

on performance with Σ-Δ converters due to the way the convert-

ers operate internally. When driving the AD7768 directly with the

ADA4255, enable the internal buffers of the AD7768. Alternatively,

a dedicated ADC driver and amplifier can be configured between

the ADA4255 and the AD7768.

In both configurations, it is recommended that two reads from the

M_CLK_CNT register are performed to ensure that the master

clock counter is incrementing, indicating that the ADA4255 is re-

ceiving an external clock.

Figure 105. Clock Synchronization with the AD4007

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