ADA4255ACPZ-R7 datasheet(2/64 Pages) AD

2 / 64 page

Data Sheet

ADA4255

TABLE OF CONTENTS

analog.com

Rev. 0 | 2 of 64

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Simplified Functional Block Diagram..................... 1

Companion Products............................................. 1

Specifications........................................................ 4

Timing Specifications......................................... 8

Absolute Maximum Ratings...................................9

Thermal Resistance........................................... 9

ESD Caution.......................................................9

Pin Configurations and Function Descriptions.....10

Typical Performance Characteristics................... 11

Theory of Operation.............................................25

Programmable Gain Instrumentation

Amplifier......................................................... 25

Input Multiplexer...............................................26

EMI Reduction and the Internal EMI Filter....... 26

Input Amplifier.................................................. 27

Output Amplifier................................................27

Power Supplies................................................ 28

ESD Map..........................................................28

Output Ripple Calibration Configuration...........29

General-Purpose Inputs and Outputs

(GPIOs).......................................................... 29

Excitation Currents........................................... 30

External Clock Synchronization .......................30

Sequential Chip Select (SCS).......................... 30

Gain Error Calibration.......................................32

Wire Break Detection....................................... 34

Test Multiplexer................................................ 35

External Mux Control........................................35

Digital Interface....................................................36

SPI....................................................................36

Accessing the ADA4255 Register Map............ 36

Checksum Protection....................................... 36

CRC Calculation...............................................38

Memory Map Checksum Protection................. 38

Read-Only Memory (ROM) Checksum

Protection....................................................... 38

SPI Read and Write Error Detection................ 38

SPI Command Length Error Detection.............38

Applications Information...................................... 39

Input and Output Offset Voltage and Noise......39

ADC Clock Synchronization............................. 39

Programmable Logic Controller (PLC)

Voltage and Current Input.............................. 41

3-Wire RTD With Current Excitation.................42

High Rail Current Sensing................................43

Gain Multiplexer Register (GAIN_MUX)

Details............................................................ 46

Software Reset Register (Reset) Details..........47

Clock Synchronization Configuration

Digital Error Register (DIGITAL_ERR)

Details............................................................ 49

Analog Error Register (ANALOG_ERR)

Details............................................................ 50

GPIO Data Register (GPIO_DATA) Details......51

Internal Mux Control Register

(INPUT_MUX) Details.................................... 52

Wire Break Detect Register (WB_DETECT)

Details............................................................ 53

GPIO Direction Register (GPIO_DIR) Details.. 54

Sequential Chip Select Register (SCS)

Details............................................................ 54

Analog Error Mask Register

(ANALOG_ERR_DIS) Details........................ 55

Digital Error Mask Register

(DIGITAL_ERR_DIS) Details..........................56

Special Function Configuration Register

(SF_CFG) Details...........................................57

Error Configuration Register (ERR_CFG)

Details............................................................ 58

Test Multiplexer Register (TEST_MUX)

Details............................................................ 59

Excitation Current Configuration Register

(EX_CURRENT_CFG) Details....................... 61

Gain Calibration Registers (GAIN_CALx)

Details............................................................ 62

Trigger Calibration Register (TRIG_CAL)

Details............................................................ 63

Master Clock Count Register

(M_CLK_CNT) Details....................................63

DIE Revision Identification Register

(DIE_REV_ID) Details.................................... 63

Device Identification Registers (PART_ID)

Details............................................................ 63

Outline Dimensions............................................. 64

Ordering Guide.................................................64

Evaluation Boards............................................ 64

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