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ADA4255ACPZ-R7 データシート(PDF) 8 Page - Analog Devices

部品番号 ADA4255ACPZ-R7
部品情報  Zero Drift, High Voltage, Programmable Gain Instrumentation Amplifier with Charge Pump
PDF  64 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADA4255ACPZ-R7 データシート(HTML) 8 Page - Analog Devices

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Data Sheet
ADA4255
SPECIFICATIONS
analog.com
Rev. 0 | 8 of 64
TIMING SPECIFICATIONS
VDDCP = 5 V, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3V, DVSS = 0 V, and VOCM = AVDD/2 V.
Table 2. Digital Values and Serial Peripheral Interface (SPI) Timing Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Maximum Clock Rate (SCLK)
5
MHz
Minimum Pulse Width (SCLK)
High
tPWH
75
ns
Low
tPWL
75
ns
SDI/SDO to SCLK Setup Time
tDS
10
ns
SDI/SDO to SCLK Hold Time
tDH
10
ns
Data Valid, SDO to SCLK
tDV
50
ns
Setup Time, CS to SCLK
tDCS
30
ns
Timing Diagrams
Figure 2. SPI Timing Diagram, MSB First
Figure 3. SPI Register Write Timing Diagram
Figure 4. SPI Register Read Timing Diagram



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