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H8SX/1663R データシート(PDF) 362 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 362 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 330 of 1468
REJ09B0412-0200
When the time between the REF command and the subsequent ACTV command does not meet a
given specification, a wait cycle can be inserted for one to seven cycles during a refresh cycle by
bits RLW2 to RLW0 in REFCR. Set the bit according to the SDRAM to be used and the
frequency of this LSI so that the number of wait cycles can be optimal.
Figure 9.78 shows a timing example when the one wait cycle is inserted.
TR
p
TR
r
TR
cw
TR
c1
TR
c2
Address bus
SDRAM
φ
CS
Precharge-sel
RAS
CAS
WE
CKE
PALL
REF
NOP
BS
RD/
WR
High
High
High
Figure 9.78 Auto-Refresh Timing (TPC1 = 0, TPC0 = 0, RLW2 = 0, RLW1 = 0, RLW0 = 1)



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