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H8SX/1663R データシート(PDF) 46 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 46 Page - Renesas Technology Corp |
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46 / 1504 page  Section 1 Overview Rev. 2.00 Sep. 24, 2008 Page 14 of 1468 REJ09B0412-0200 11 10 10 914 15 13 12 8 7 6 5 4 3 2 1 11 PB1 PB3 Vcc NC*3 PM2 PF6 Vss PF0 Vss PE3*1 PE0*1 Vss PD4*1 PD1*1 EMLE*2 PC3 MD0 P64 P37 P17 WDTOVF RES NC*3 P13 PI7 PI3 Vss PH2 PH1 PH0 PLLVcc P61 P36 STBY Vcc XTAL P14 OSC2 Vss P11 PI6 Vss PI1 Vcc PH7 NC*3 P62 P60 Vss P16 EXTAL P15 OSC1 NC*3 P12 PI5 PI2 NC*3 PH6 PH5 P65 PLLVss P63 P35 NC*3 Vss VCL NC*3 Vss P10 PI4 PI0 Vss PH4 PH3 PA1 PA2 PA0 PA3 NC*3 NC*3 DrVss VBUS NC*3 MD1 NC*3 NC*3 P80 MD_CLK NC*3 Vss NC*3 AVcc P53 NC*3 P52 P31 P32 P27 P26 P51 P50 NC*3 PC2 Vcc NMI P34 P33 Vref NC*3 P54 AVss P23 P23 P24 P30 P25 P57 NC*3 P56 P55 P20 Vcc P22 P21 PB6 MD3 PB5 PB4 NC*3 NC*3 NC*3 NC*3 PA4 PA5 PA6 Vss PM0 NC*3 PF4 PF2 PE6*1 Vcc PD6*1 PD3*1 PM4 USD+ USD- Vcc PA7 PB2 PB7 PM1 PF7 PF3 PF1 PE5*1 NC*3 PE1*1 PD5*1 NC*3 NC*3 DrVcc Vcc PB0 Vss MD2 NC*3 PF5 Vss PE7*1 PE4*1 PE2*1 PD7*1 Vss PD2*1 PD0*1 PM3 914 15 13 12 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R A B C D E F G H J K L M N P R LFBGA-176 (Upper perspective view) Notes: 1. In single-chip mode ports D and E can be used (initial state). Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value) and ports J and K are enabled when PCJKE = 1. In external extended mode, only ports D and E can be used. 2. This pin is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode. The on-chip emulator function is enabled by driving this pin high. When the on-chip emulator is in use, the P62, P63, P64, P65, and WDTOVF pins are dedicated pins for the on-chip emulator. For details on a connection example with the E10A, see E10A Emulator User's Manual. 3. The NC (no-connection) pin should be left open. Figure 1.4 Pin Assignments (LFBGA-176) |
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