H8SXSLASH1663R datasheet(81/1504 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 49 of 1468

REJ09B0412-0200

2.6.2

Memory Data Formats

Figure 2.13 shows the data formats in memory.

The H8SX CPU can access word data and longword data which are stored at any addresses in

memory. When word data begins at an odd address or longword data begins at an address other

than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when

longword data begins at an odd address, the bus cycle is divided into byte, word, and byte

accesses. In this case, these accesses are assumed to be individual bus cycles.

However, instructions to be fetched, word and longword data to be accessed during execution of

the stack manipulation, branch table manipulation, block transfer instructions, and MAC

instruction should be located to even addresses.

When SP (ER7) is used as an address register to access the stack, the operand size should be word

size or longword size.

654

MSB

LSB

MSB

LSB

MSB

LSB

Data Type

Data Format

1-bit data

Byte data

Word data

Longword data

Address

Address L

Address 2M

Address 2M + 1

Address 2N

Address 2N + 1

Address 2N + 2

Address 2N + 3

Figure 2.13 Memory Data Formats

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