H8SXSLASH1663R datasheet(25/1504 Pages) RENESAS

25 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xxv of xxxii

19.10.4

Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) ................................................................. 953

19.10.5

Relation between Writing to TDR and TDRE Flag .......................................... 954

19.10.6

Restrictions on Using DTC or DMAC.............................................................. 954

19.10.7

SCI Operations during Power-Down State ....................................................... 955

19.11 CRC Operation Circuit ..................................................................................................... 958

19.11.1

Features............................................................................................................. 958

19.11.2

19.11.3

CRC Operation Circuit Operation..................................................................... 961

19.11.4

Note on CRC Operation Circuit........................................................................ 964

Section 20 USB Function Module (USB)..........................................................965

20.1

Features............................................................................................................................. 965

20.2

Input/Output Pins.............................................................................................................. 966

20.3

Register Descriptions ........................................................................................................ 967

20.3.1

Interrupt Flag Register 0 (IFR0) ....................................................................... 968

20.3.2

Interrupt Flag Register 1 (IFR1) ....................................................................... 970

20.3.3

Interrupt Flag Register 2 (IFR2) ....................................................................... 971

20.3.4

Interrupt Select Register 0 (ISR0)..................................................................... 973

20.3.5

Interrupt Select Register 1 (ISR1)..................................................................... 974

20.3.6

Interrupt Select Register 2 (ISR2)..................................................................... 975

20.3.7

Interrupt Enable Register 0 (IER0) ................................................................... 976

20.3.8

Interrupt Enable Register 1 (IER1) ................................................................... 977

20.3.9

Interrupt Enable Register 2 (IER2) ................................................................... 977

20.3.10

EP0i Data Register (EPDR0i) ........................................................................... 978

20.3.11

EP0o Data Register (EPDR0o) ......................................................................... 979

20.3.12

EP0s Data Register (EPDR0s) .......................................................................... 979

20.3.13

EP1 Data Register (EPDR1) ............................................................................. 980

20.3.14

EP2 Data Register (EPDR2) ............................................................................. 980

20.3.15

EP3 Data Register (EPDR3) ............................................................................. 981

20.3.16

EP0o Receive Data Size Register (EPSZ0o) .................................................... 981

20.3.17

EP1 Receive Data Size Register (EPSZ1) ........................................................ 982

20.3.18

Trigger Register (TRG)..................................................................................... 982

20.3.19

Data Status Register (DASTS).......................................................................... 984

20.3.20

FIFO Clear Register (FCLR) ............................................................................ 985

20.3.21

DMA Transfer Setting Register (DMA) ........................................................... 986

20.3.22

Endpoint Stall Register (EPSTL)...................................................................... 989

20.3.23

Configuration Value Register (CVR) ............................................................... 990

20.3.24

Control Register (CTLR) .................................................................................. 990

20.3.25

Endpoint Information Register (EPIR) ............................................................. 992

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