H8SXSLASH1663R datasheet(17/1504 Pages) RENESAS

17 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xvii of xxxii

Section 11 EXDMA Controller (EXDMAC) ....................................................453

11.1

Features............................................................................................................................. 453

11.2

Input/Output Pins.............................................................................................................. 456

11.3

Registers Descriptions ...................................................................................................... 457

11.3.1

EXDMA Source Address Register (EDSAR)................................................... 459

11.3.2

EXDMA Destination Address Register (EDDAR) ........................................... 460

11.3.3

EXDMA Offset Register (EDOFR) .................................................................. 461

11.3.4

EXDMA Transfer Count Register (EDTCR).................................................... 462

11.3.5

EXDMA Block Size Register (EDBSR)........................................................... 463

11.3.6

EXDMA Mode Control Register (EDMDR) .................................................... 464

11.3.7

EXDMA Address Control Register (EDACR) ................................................. 473

11.3.8

Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7).................................... 479

11.4

Transfer Modes ................................................................................................................. 480

11.4.1

Ordinary Modes ................................................................................................ 480

11.4.2

Cluster Transfer Modes..................................................................................... 481

11.5

Mode Operation ................................................................................................................ 482

11.5.1

Address Modes ................................................................................................. 482

11.5.2

Transfer Modes ................................................................................................. 485

11.5.3

Activation Sources ............................................................................................ 490

11.5.4

Bus Mode.......................................................................................................... 491

11.5.5

Extended Repeat Area Function ....................................................................... 492

11.5.6

Address Update Function Using Offset ............................................................ 495

11.5.7

Registers during EXDMA Transfer Operation ................................................. 499

11.5.8

Channel Priority Order...................................................................................... 504

11.5.9

Basic Bus Cycles .............................................................................................. 505

11.5.10

Bus Cycles in Dual Address Mode ................................................................... 506

11.5.11

Bus Cycles in Single Address Mode................................................................. 515

11.5.12

Operation Timing in Each Mode ...................................................................... 520

11.6

Operation in Cluster Transfer Mode ................................................................................. 531

11.6.1

Address Mode ................................................................................................... 531

11.6.2

Setting of Address Update Mode ...................................................................... 536

11.6.3

Caution for Combining with Extended Repeat Area Function ......................... 537

11.6.4

Bus Cycles in Cluster Transfer Dual Address Mode ........................................ 537

11.6.5

Operation Timing in Cluster Transfer Mode .................................................... 540

11.7

Ending EXDMA Transfer................................................................................................. 548

11.8

Relationship among EXDMAC and Other Bus Masters................................................... 551

11.8.1

CPU Priority Control Function Over EXDMAC .............................................. 551

11.8.2

Bus Arbitration with Another Bus Master ........................................................ 552

11.9

Interrupt Sources...............................................................................................................553

11.10 Usage Notes ...................................................................................................................... 556

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