H8SXSLASH1663R datasheet(72/1504 Pages) RENESAS

部品番号	H8SX/1663R

部品情報	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

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メーカー	RENESAS [Renesas Technology Corp]

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Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 40 of 1468

REJ09B0412-0200

H'00000000

H'00000003

H'00000004

Exception vector table

Reset exception vector

H'00000007

H'00000001

H'00000002

H'00000005

H'00000006

Figure 2.6 Exception Vector Table (Maximum Modes)

The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes

are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction

code specifies a memory location. Execution branches to the contents of the memory location.

In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch

address.

• Stack Structure

The stack structure of PC at a subroutine branch and that of PC and CCR at an exception

handling are shown in figure 2.7. The PC contents are saved or restored in 32-bit units. The

EXR contents are saved or restored regardless of whether or not EXR is in use.

(a) Subroutine Branch

(b) Exception Handling

(32 bits)

EXR

CCR

(32 bits)

Figure 2.7 Stack Structure (Maximum Mode)

H8SX/1663R データシート(PDF) 72 Page - Renesas Technology Corp