H8SXSLASH1663R datasheet(15/1504 Pages) RENESAS

15 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xv of xxxii

9.10

DRAM Interface ............................................................................................................... 280

9.10.1

Setting DRAM Space........................................................................................ 280

9.10.2

Address Multiplexing........................................................................................ 280

9.10.3

Data Bus............................................................................................................ 281

9.10.4

I/O Pins Used for DRAM Interface .................................................................. 281

9.10.5

Basic Timing..................................................................................................... 282

9.10.6

Controlling Column Address Output Cycle...................................................... 283

9.10.7

Controlling Row Address Output Cycle ........................................................... 284

9.10.8

Controlling Precharge Cycle............................................................................. 286

9.10.9

Wait Control ..................................................................................................... 287

9.10.10

Controlling Byte and Word Accesses ............................................................... 290

9.10.11

Burst Access Operation..................................................................................... 292

9.10.12

Refresh Control................................................................................................. 298

9.10.13

DRAM Interface and Single Address Transfer by DMAC and EXDMAC ...... 303

9.11

Synchronous DRAM Interface ......................................................................................... 306

9.11.1

Setting SDRAM space ...................................................................................... 306

9.11.2

Address Multiplexing........................................................................................ 307

9.11.3

Data Bus............................................................................................................ 307

9.11.4

I/O Pins Used for DRAM Interface .................................................................. 308

9.11.5

Basic Timing..................................................................................................... 309

9.11.6

CAS Latency Control........................................................................................ 311

9.11.7

Controlling Row Address Output Cycle ........................................................... 313

9.11.8

Controlling Precharge Cycle............................................................................. 315

9.11.9

Controlling Clock Suspend Insertion ................................................................ 317

9.11.10

Controlling Write-Precharge Delay .................................................................. 318

9.11.11

Controlling Byte and Word Accesses ............................................................... 319

9.11.12

Fast-Page Access Operation ............................................................................. 321

9.11.13

Refresh Control................................................................................................. 327

9.11.14

Setting SDRAM Mode Register ....................................................................... 335

9.11.15

SDRAM Interface and Single Address Transfer by DMAC and EXDMAC .... 336

9.11.16

EXDMAC Cluster Transfer .............................................................................. 344

9.12

Idle Cycle.......................................................................................................................... 347

9.12.1

Operation .......................................................................................................... 347

9.12.2

Pin States in Idle Cycle ..................................................................................... 359

9.13

Bus Release....................................................................................................................... 360

9.13.1

Operation .......................................................................................................... 360

9.13.2

Pin States in External Bus Released State......................................................... 361

9.13.3

Transition Timing ............................................................................................. 362

9.14

Internal Bus....................................................................................................................... 364

9.14.1

Access to Internal Address Space ..................................................................... 364

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