H8SXSLASH1663R datasheet(57/1504 Pages) RENESAS

57 / 1504 page

Section 1 Overview

Rev. 2.00 Sep. 24, 2008 Page 25 of 1468

REJ09B0412-0200

Classification

Pin Name

I/O

Description

CS0

CS1

CS2-A/CS2-B

CS3-A

CS4-A/CS4-B

CS5-A/CS5-B/

CS5-D

CS6-A/CS6-B/

CS6-D

CS7-A/CS7-B

Output

Select signals for areas 0 to 7.

WAIT

Input

Requests wait cycles in access to the external space.

RAS

Output

•

Row address strobe signal for the DRAM when area 2

is specified as the DRAM interface space

•

Row address strobe signal for the synchronous DRAM

when area 2 is specified as the synchronous DRAM

interface space

CAS

Output

•

Column address strobe signal for the synchronous

DRAM when area 2 is specified as the synchronous

DRAM interface space

Output

•

Write enable signal for the DRAM space

•

Synchronous DRAM write enable signal when area 2 is

specified as the synchronous DRAM interface space

OE/CKE

Output

•

Output enable signal for the DRAM interface space

•

Clock enable signal for the synchronous DRAM

interface space

LUCAS

Output

•

Upper column address strobe signal for the 16-bit

DRAM interface space

LLCAS

Output

•

Lower column address strobe signal for the 16-bit

DRAM interface space

•

Column address strobe signal for the 8-bit DRAM

interface space

DQMLU

Output

•

Upper data mask enable signal for the 16-bit

synchronous DRAM interface space

Bus control

DQMLL

Output

•

Lower data mask enable signal for the 16-bit

synchronous DRAM interface space

•

Data mask enable signal for the 8-bit synchronous

DRAM interface space

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