H8SXSLASH1663R datasheet(59/1504 Pages) RENESAS

59 / 1504 page

Section 1 Overview

Rev. 2.00 Sep. 24, 2008 Page 27 of 1468

REJ09B0412-0200

Classification

Pin Name

I/O

Description

EDREQ0-A/

EDREQ0-B

EDREQ1-A/

EDREQ1-B

EDREQ2

EDREQ3

Input

Requests EXDMAC activation.

EDACK0-A/

EDACK0-B

EDACK1-A/

EDACK1-B

EDACK2

EDACK3

Output

EXDMAC single address-transfer acknowledge signal.

ETEND0-A/

ETEND0-B

ETEND1-A/

ETEND1-B

ETEND2

ETEND3

Output

Indicates end of data transfer by the EXDMAC.

EXDMA

controller

(EXDMAC)

EDRAK0

EDRAK1

Output

Notification to external device of EXDMAC external request

acceptance and start of execution.

TCLKA-A/TCLKA-B

TCLKB-A/TCLKB-B

TCLKC-A/TCLKC-B

TCLKD-A/TCLKD-B

Input

Input pins for the external clock signals.

TIOCA0

TIOCB0

TIOCC0

TIOCD0

Input/

output

Signals for TGRA_0 to TGRD_0. These pins are used as

input capture inputs, output compare outputs, or PWM

outputs.

TIOCA1

TIOCB1

Input/

output

Signals for TGRA_1 and TGRB_1. These pins are used as

input capture inputs, output compare outputs, or PWM

outputs.

TIOCA2

TIOCB2

Input/

output

Signals for TGRA_2 and TGRB_2. These pins are used as

input capture inputs, output compare outputs, or PWM

outputs.

TIOCA3

TIOCB3

TIOCC3

TIOCD3

Input/

output

Signals for TGRA_3 to TGRD_3. These pins are used as

input capture inputs, output compare outputs, or PWM

outputs.

16-bit timer

pulse unit (TPU)

TIOCA4

TIOCB4

Input/

output

Signals for TGRA_4 and TGRB_4. These pins are used as

input capture inputs, output compare outputs, or PWM

outputs.

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