H8SXSLASH1663R datasheet(78/1504 Pages) RENESAS

78 / 1504 page

Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 46 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

Undefined

R/W

Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to

indicate non-zero data.

Undefined

R/W

Overflow Flag

Set to 1 when an arithmetic overflow occurs, and

cleared to 0 otherwise.

Undefined

R/W

Carry Flag

Set to 1 when a carry occurs, and cleared to 0

otherwise. A carry has the following types:

•

Carry from the result of addition

•

Borrow from the result of subtraction

•

Carry from the result of shift or rotation

The carry flag is also used as a bit accumulator by bit

manipulation instructions.

2.5.4

Extended Control Register (EXR)

EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0).

Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC

instructions.

For details, see section 6, Exception Handling.

Bit

Bit Name

Initial

Value

R/W

Description

R/W

Trace Bit

When this bit is set to 1, a trace exception is generated

each time an instruction is executed. When this bit is

cleared to 0, instructions are executed in sequence.

6 to 3

—

All 1

R/W

Reserved

These bits are always read as 1.

R/W

Interrupt Mask Bits

These bits designate the interrupt mask level (0 to 7).

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