H8SXSLASH1663R datasheet(73/1504 Pages) RENESAS

部品番号	H8SX/1663R

部品情報	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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メーカー	RENESAS [Renesas Technology Corp]

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Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 41 of 1468

REJ09B0412-0200

2.3

Instruction Fetch

The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended

that the mode be set according to the bus width of the memory in which a program is stored. The

instruction-fetch mode setting does not affect operation other than instruction fetch such as data

accesses. Whether an instruction is fetched in 16- or 32-bit mode is selected by the FETCHMD bit

in SYSCR. For details, see section 3.2.2, System Control Register (SYSCR).

2.4

Address Space

Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the

CPU operating mode.

H'0000

H'000000

H'007FFF

H'FF8000

H'FFFFFF

H'00000000

H'00FFFFFF

H'FFFFFFFF

H'00000000

H'FFFFFFFF

H'FFFF

Normal mode

Program area

Data area

(64 kbytes)

Program area

Data area

(4 Gbytes)

Program area

(16 Mbytes)

Program area

(16 Mbytes)

Data area

(64 kbytes)

Data area

(4 Gbytes)

Middle mode

Advanced mode

Maximum mode

Figure 2.8 Memory Map

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