H8SXSLASH1663R datasheet(14/1504 Pages) RENESAS

14 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xiv of xxxii

9.5.3

Chip Select Signals ........................................................................................... 230

9.5.4

External Bus Interface ...................................................................................... 231

9.5.5

Area and External Bus Interface ....................................................................... 236

9.5.6

Endian and Data Alignment.............................................................................. 241

9.6

Basic Bus Interface ........................................................................................................... 244

9.6.1

Data Bus ........................................................................................................... 244

9.6.2

I/O Pins Used for Basic Bus Interface .............................................................. 244

9.6.3

Basic Timing..................................................................................................... 245

9.6.4

Wait Control ..................................................................................................... 251

9.6.5

Read Strobe (

RD) Timing................................................................................. 253

9.6.6

Extension of Chip Select (

CS) Assertion Period............................................... 254

9.6.7

DACK and EDACK Signal Output Timing...................................................... 256

9.7

Byte Control SRAM Interface .......................................................................................... 257

9.7.1

Byte Control SRAM Space Setting................................................................... 257

9.7.2

Data Bus ........................................................................................................... 257

9.7.3

I/O Pins Used for Byte Control SRAM Interface ............................................. 258

9.7.4

Basic Timing..................................................................................................... 259

9.7.5

Wait Control ..................................................................................................... 261

9.7.6

Read Strobe (

RD) ............................................................................................. 263

9.7.7

Extension of Chip Select (

CS) Assertion Period............................................... 263

9.7.8

DACK and EDACK Signal Output Timing...................................................... 263

9.8

Burst ROM Interface ........................................................................................................ 265

9.8.1

Burst ROM Space Setting................................................................................. 265

9.8.2

Data Bus ........................................................................................................... 265

9.8.3

I/O Pins Used for Burst ROM Interface............................................................ 266

9.8.4

Basic Timing..................................................................................................... 267

9.8.5

Wait Control ..................................................................................................... 269

9.8.6

Read Strobe (

RD) Timing................................................................................. 269

9.8.7

Extension of Chip Select (

CS) Assertion Period............................................... 269

9.9

Address/Data Multiplexed I/O Interface........................................................................... 270

9.9.1

Address/Data Multiplexed I/O Space Setting ................................................... 270

9.9.2

Address/Data Multiplex .................................................................................... 270

9.9.3

Data Bus ........................................................................................................... 270

9.9.4

I/O Pins Used for Address/Data Multiplexed I/O Interface.............................. 271

9.9.5

Basic Timing..................................................................................................... 272

9.9.6

Address Cycle Control...................................................................................... 274

9.9.7

Wait Control ..................................................................................................... 275

9.9.8

Read Strobe (

RD) Timing................................................................................. 275

9.9.9

Extension of Chip Select (

CS) Assertion Period............................................... 277

9.9.10

DACK and EDACK Signal Output Timing...................................................... 279

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