H8SXSLASH1663R datasheet(44/1504 Pages) RENESAS

44 / 1504 page

Section 1 Overview

Rev. 2.00 Sep. 24, 2008 Page 12 of 1468

REJ09B0412-0200

1.3

Block Diagram

External bus

[Legend]

CPU:

DTC:

BSC:

DMAC:

EXDMAC:

TM32K:

WDT:

Central processing unit

Data transfer controller

Bus controller

DMA controller

EXDMA controller

32K timer

Watchdog timer

8-bit timer

16-bit timer pulse unit

Programmable pulse generator

Serial communications interface

Universal serial bus interface

IIC bus interface 2

Power-on reset / Low voltage detection circuit

TMR:

TPU:

PPG:

SCI:

USB:

IIC2:

POR/LVD*2:

Interrupt

controller

H8SX

CPU

RAM

ROM

DTC

Main clock

oscillator

Subclock

oscillator

POR/LVD*2

BSC

DMAC

4 channels

EXDMAC

4 channels

TMR

× 2 channels

(unit 1)

TMR

× 2 channels

(unit 0)

TMR

× 2 channels

(unit 3)

TMR

× 2 channels

(unit 2)

TM32K

WDT

TPU

× 6 channels

(unit 0)

TPU

× 6 channels

(unit 1)

PPG

× 16 channels

(unit 0)

PPG

× 16 channels

(unit 1)

10-bit AD

× 4

channels (unit 0)

10-bit AD

× 4

channels (unit 1)

SCI

× 6 channels

IIC2

× 2 channels

Port 1

Port 2

Port M

Port 6

Port A

Port B

Port C

Port D/

port J*1

Port E/

port K*1

Port F

Port H

Port I

8-bit DA

2 channels

Port 5

Port 3

USB

Note:

In single-chip mode, the port D and port E functions can be used in the initial state.

Pin functions are selectable by setting the PCJKE bit in PFCRD.

Ports D and E are enabled when PCJKE=0 (initial value) and ports J and K are enabled

when PCJKE=1.

In external extended mode, only ports D and E can be used.

Supported only by the H8SX/1668MGroup.

Figure 1.2 Block Diagram

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