H8SXSLASH1663R datasheet(16/1504 Pages) RENESAS

16 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xvi of xxxii

9.15

Write Data Buffer Function .............................................................................................. 365

9.15.1

Write Data Buffer Function for External Data Bus .......................................... 365

9.15.2

Write Data Buffer Function for Peripheral Modules ........................................ 366

9.16

Bus Arbitration .................................................................................................................367

9.16.1

Operation .......................................................................................................... 367

9.16.2

Bus Transfer Timing......................................................................................... 368

9.17

Bus Controller Operation in Reset .................................................................................... 371

9.18

Usage Notes ...................................................................................................................... 371

Section 10 DMA Controller (DMAC)............................................................... 375

10.1

Features............................................................................................................................. 375

10.2

Input/Output Pins.............................................................................................................. 378

10.3

Register Descriptions........................................................................................................ 379

10.3.1

DMA Source Address Register (DSAR) .......................................................... 380

10.3.2

DMA Destination Address Register (DDAR) .................................................. 381

10.3.3

DMA Offset Register (DOFR).......................................................................... 382

10.3.4

DMA Transfer Count Register (DTCR) ........................................................... 383

10.3.5

DMA Block Size Register (DBSR) .................................................................. 384

10.3.6

DMA Mode Control Register (DMDR)............................................................ 385

10.3.7

DMA Address Control Register (DACR) ......................................................... 394

10.3.8

DMA Module Request Select Register (DMRSR) ........................................... 400

10.4

Transfer Modes................................................................................................................. 401

10.5

Operations......................................................................................................................... 402

10.5.1

Address Modes ................................................................................................. 402

10.5.2

Transfer Modes ................................................................................................. 406

10.5.3

Activation Sources............................................................................................ 411

10.5.4

Bus Access Modes ............................................................................................ 413

10.5.5

Extended Repeat Area Function ....................................................................... 415

10.5.6

Address Update Function using Offset ............................................................. 418

10.5.7

10.5.8

Priority of Channels .......................................................................................... 427

10.5.9

DMA Basic Bus Cycle...................................................................................... 429

10.5.10

Bus Cycles in Dual Address Mode ................................................................... 430

10.5.11

Bus Cycles in Single Address Mode................................................................. 439

10.6

DMA Transfer End ........................................................................................................... 444

10.7

Relationship among DMAC and Other Bus Masters ........................................................ 447

10.7.1

CPU Priority Control Function Over DMAC ................................................... 447

10.7.2

Bus Arbitration among DMAC and Other Bus Masters ................................... 448

10.8

Interrupt Sources...............................................................................................................449

10.9

Usage Notes ...................................................................................................................... 452

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