H8SXSLASH1663R datasheet(39/1504 Pages) RENESAS

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Section 1 Overview

Rev. 2.00 Sep. 24, 2008 Page 7 of 1468

REJ09B0412-0200

Classification

Module/

Function

Description

16-bit timer

pulse unit

(TPU)

• 16 bits × 12 channels (unit 0, unit 1*)

• Select from among eight counter-input clocks for each channel

• Up to 16 pulse inputs and outputs

• Counter clear operation, simultaneous writing to multiple timer

counters (TCNT), simultaneous clearing by compare match and

input capture possible, simultaneous input/output for registers

possible by counter synchronous operation, and up to 15-phase

PWM output possible by combination with synchronous

operation

• Buffered operation, cascaded operation (32 bits × two

channels), and phase counting mode (two-phase encoder

input) settable for each channel

• Input capture function supported

• Output compare function (by the output of compare match

waveform) supported

Note:

Pin function of unit 1 cannot be used in the external bus

extended mode.

Timer

Program-

mable pulse

generator

(PPG)

• 32-bit*1*2 pulse output

• Four output groups, non-overlapping mode, and inverted output

can be set

• Selectable output trigger signals; the PPG can operate in

conjunction with the data transfer controller (DTC) and the DMA

controller (DMAC)

Notes: 1. Pulse output pins PO31 to PO16 cannot be activated by

input capture.

2. Pulse of unit 1 cannot be output in external bus

extended mode.

Watchdog timer Watchdog

timer

(WDT)

• 8 bits × one channels (selectable from eight counter input

clocks)

• Switchable between watchdog timer mode and interval timer

mode

32K timer

(TM32K)

• Eight counter clocks which divides the 32.768 Hz clock can be

selected

• 8 bits × 1 channel or 24 bits × 1 channel can be selected

• Interrupts can be generated when the counter overflows.

• Eight overflow cycles selectable (250 msec, 500 msec, 1 sec, 2

sec, 30 sec, 60 sec, about 23 days, and about 46 days)

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