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H8SX/1663R データシート(PDF) 369 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 369 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 337 of 1468
REJ09B0412-0200
(1)
When DDS = 1 or EDDS = 1
A fast-page access is performed regardless of the bus master, only according to the address. The
DACK and EDACK signals are asserted within the Tc1 cycle in both read and write accesses.
Figures 9.83 and 9.84 show the output timing example of the
DACK and EDACK signals when
DDS = 1 or EDDS = 1.
T
p
T
r
T
c1
T
c2
T
c1
T
c2
CS
Precharge-sel
RAS
CAS
WE
CKE
PALL
ACTV
NOP
NOP
WRIT
WRIT
DQMLU
DQMLL
D7 to D0
BS
DACK or EDACK
RD/
WR
D15 to D8
Address bus
Row address
Row
address
Column address 1
Column address 2
SDRAM
φ
High
Figure 9.83 Output Timing Example of
DACK and EDACK when DDS = 1 or EDDS = 1
(Write)



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