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H8SX/1663R データシート(PDF) 376 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 376 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 344 of 1468
REJ09B0412-0200
T
p
T
r
T
c1
T
c2
Address bus
Row address
Cloumn address
SDRAM
φ
CS
Precharge-sel
RAS
CAS
WE
CKE
PALL
ACTV
WRIT
NOP
DQMLU
DQMLL
D7 to D0
BS
RD/
WR
D15 to D8
Row
address
High
DACK or EDACK
Figure 9.90 Output Timing Example of
DACK and EDACK when DKC = 1 or EDKC = 1
and DDS = 0 or EDDS = 0 (Write)
9.11.16
EXDMAC Cluster Transfer
Using an EXDMAC cluster transfer mode, data can be read from or written to consecutively. For
details, see section 11, EXDMA Controller (EXDMAC).
Figures 9.91 and 9.92 show a read/write timing using a cluster transfer.
For 1-cycle read or write, set the BE bit in DRAMCR to 1, clear the TRWL bit in SDCR to 0, and
set the CAS latency to 2. During a read cycle, the clock suspend mode cannot be used.
Do not change the bus controller register settings during a cluster transfer.



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