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H8SX/1663R データシート(PDF) 511 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 511 Page - Renesas Technology Corp |
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511 / 1504 page  Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 479 of 1468 REJ09B0412-0200 11.3.8 Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7) CLSBR0 to CLSBR7 are 32-bit readable/writable registers that store the transfer data. The transfer data is stored in order from CLSBR0 to CLSBR7 in cluster transfer mode. The data stored in cluster transfer mode or by the CPU write operation is held until the next cluster transfer or CPU write operation is performed. When reading the data stored in cluster transfer mode by the CPU, check the completion of cluster transfer and then perform only a cluster-size read specified for the cluster transfer. Data with another size is undefined. In cluster transfer mode, the same CLSBR is used for all channels. When the CPU write operation to CLSBR conflicts with cluster transfer, the contents of transferred data are not guaranteed. When cluster transfer read/write address mode is specified and if another channel is set for cluster transfer, the transferred data may be overwritten. 31 Undefined R/W 30 Undefined R/W 29 Undefined R/W 28 Undefined R/W 27 Undefined R/W 24 Undefined R/W 26 Undefined R/W 25 Undefined R/W Bit Bit Name Initial Value R/W 23 Undefined R/W 22 Undefined R/W 21 Undefined R/W 20 Undefined R/W 19 Undefined R/W 16 Undefined R/W 18 Undefined R/W 17 Undefined R/W Bit Bit Name Initial Value R/W 15 Undefined R/W 14 Undefined R/W 13 Undefined R/W 12 Undefined R/W 11 Undefined R/W 8 Undefined R/W 10 Undefined R/W 9 Undefined R/W Bit Bit Name Initial Value R/W 7 Undefined R/W 6 Undefined R/W 5 Undefined R/W 4 Undefined R/W 3 Undefined R/W 0 Undefined R/W 2 Undefined R/W 1 Undefined R/W Bit Bit Name Initial Value R/W |
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