H8SXSLASH1663R datasheet(517/1504 Pages) RENESAS

部品番号	H8SX/1663R

部品情報	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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メーカー	RENESAS [Renesas Technology Corp]

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Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 485 of 1468

REJ09B0412-0200

Address T

Address B

EDACK

Transfer

Figure 11.6 Single Address Mode Operation

11.5.2

Transfer Modes

(1)

Normal Transfer Mode

In normal transfer mode, transfer of one data access size unit is processed in response to one

transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. EDBSR is invalid

in normal transfer mode.

The

ETEND signal is output only for the last EXDMA transfer. The EDRAK signal is output each

time a transfer request is accepted and transfer processing is started.

Figure 11.7 shows examples of transfer timing in normal transfer mode and figure 11.8 shows the

normal transfer mode operation in dual address mode.

Read

Write

Read

Write

EXDMA transfer

cycle

Last EXDMA

transfer cycle

Bus cycle

Transfer conditions: Dual address mode, auto-request mode

Transfer conditions: Single address mode, external request mode

ETEND

EDREQ

EDACK

EXDMA

Bus cycle

EDRAK

Figure 11.7 Examples of Timing in Normal Transfer Mode

H8SX/1663R データシート(PDF) 517 Page - Renesas Technology Corp

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