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H8SX/1663R データシート(PDF) 875 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 875 Page - Renesas Technology Corp

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Section 16 8-Bit Timers (TMR)
Rev. 2.00 Sep. 24, 2008 Page 843 of 1468
REJ09B0412-0200
16.8.7
Mode Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
mode and compare match count mode simultaneously.
16.8.8
Module Stop State Setting
Operation of the TMR can be disabled or enabled using the module stop control register. The
initial setting is for operation of the TMR to be halted. Register access is enabled by clearing the
module stop state. For details, see section 28, Power-Down Modes.
16.8.9
Interrupts in Module Stop State
If the module stop state is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be
disabled before entering the module stop state.



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