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H8SX/1663R データシート(PDF) 932 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 932 Page - Renesas Technology Corp

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Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Rev. 2.00 Sep. 24, 2008 Page 900 of 1468
REJ09B0412-0200
Table 19.7
BRR Settings for Various Bit Rates (Clocked Synchronous Mode)*
2
Operating Frequency P
φ (MHz)
8
10
16
20
25
30
33
35
Bit Rate
(bit/s)
n
N
n
N
n
N
n
N
n
N
n
N
n
N
n
N
110
250
3
124 —
—
3
249
500
2
249 —
—
3
124 —
—
3
233
1k
2
124 —
—
2
249 —
—
3
97
3
116 3
128 3
136
2.5k
1
199 1
249 2
99
2
124 2
155 2
187 2
205 2
218
5k
1
99
1
124 1
199 1
249 2
77
2
93
2
102 2
108
10k
0
199 0
249 1
99
1
124 1
155 1
187 1
205 1
218
25k
0
79
0
99
0
159 0
199 0
249 1
74
1
82
1
87
50k
0
39
0
49
0
79
0
99
0
124 0
149 0
164 0
174
100k
0
19
0
24
0
39
0
49
0
62
0
74
0
82
0
87
250k
0
7
0
9
0
15
0
19
0
24
0
29
0
32
0
34
500k
0
3
0
4
0
7
0
9
—
—
0
14
—
—
—
—
1M
0
1
0
3
0
4
—
—
—
—
—
—
—
—
2.5M
0
0*
1
0
1
—
—
0
2
—
—
—
—
5M
0
0*
1
—
—
—
—
—
—
—
—
[Legend]
Space: Setting prohibited.
:
Can be set, but there will be error.
Notes: 1. Continuous transmission or reception is not possible.
2. No clocked synchronous mode exists in SCI_5 and SCI_6.
Table 19.8
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)*
P
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
P
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
8
1.3333
1333333.3
20
3.3333
3333333.3
10
1.6667
1666666.7
25
4.1667
4166666.7
12
2.0000
2000000.0
30
5.0000
5000000.0
14
2.3333
2333333.3
33
5.5000
5500000.0
16
2.6667
2666666.7
35
5.8336
5833625.0
18
3.0000
3000000.0
Note
*
No clocked synchronous mode exists in SCI_5 and SCI_6.



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