データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

H8SX/1663R データシート(PDF) 1475 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 1475 Page - Renesas Technology Corp

Back Button H8SX/1663R Datasheet HTML 1471Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 1472Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 1473Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 1474Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 1475Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 1476Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 1477Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 1478Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 1479Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 1475 / 1504 page
background image
Main Revisions and Additions in this Edition
Rev. 2.00 Sep. 24, 2008 Page 1443 of 1468
REJ09B0412-0200
Item
Page
Revision (See Manual for Details)
1246
Amended
DPSBYCR controls deep software standby mode.
DPSBYCR is not initialized by the internal reset signal upon
exit from deep software standby mode.
1248
Amended
Descriptions for bit 5 in the register table:
On-chip RAM Power Off 2
RAMCUT 2, 1, and 0 control the internal power supply to
the on-chip RAM and USB in deep software standby mode.
For details, see descriptions of the RAMCUT0 bit
Amended
Descriptions for bit 4 in the register table:
On-chip RAM Power Off 1
RAMCUT 2, 1, and 0 control the internal power supply to
the on-chip RAM and USB in deep software standby mode.
For details, see descriptions of the RAMCUT0 bit.
28.2.4 Deep Standby Control
Register (DPSBYCR)
Amended
Descriptions for bit 0 in the register table:
On-chip RAM Power Off 0
RAMCUT 2, 1, and 0 control the internal power supply to
the on-chip RAM and USB in deep software standby
mode. For details, see descriptions of the RAMCUT0 bit.
28.2.5 Deep Standby Wait
Control Register (DPSWCR)
1249
Amended
DPSWCR is not initialized by the internal reset signal upon
exit from deep software standby mode.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com