H8SXSLASH1663R datasheet(176/1504 Pages) RENESAS

176 / 1504 page

Section 7 Interrupt Controller

Rev. 2.00 Sep. 24, 2008 Page 144 of 1468

REJ09B0412-0200

7.3.6

IRQ Status Register (ISR)

ISR is an IRQ15, IRQ14, and IRQ11 to IRQ0 interrupt request register.

Bit

Bit Name

Initial Value

R/W

IRQ15F

R/(W)*1

IRQ14F*2

R/(W)*1



R/(W)*1



R/(W)*1

IRQ11F

R/(W)*1

IRQ10F

R/(W)*1

IRQ9F

R/(W)*1

IRQ8F

R/(W)*1

Bit

Bit Name

Initial Value

R/W

Note:

1. Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should

be used to clear the flag.

2. Supported only by the H8SX/1668M Group.

IRQ7F

R/(W)*1

IRQ6F

R/(W)*1

IRQ5F

R/(W)*1

IRQ4F

R/(W)*1

IRQ3F

R/(W)*1

IRQ2F

R/(W)*1

IRQ1F

R/(W)*1

IRQ0F

R/(W)*1

Bit

Bit Name

Initial

Value

R/W

Description

IRQ15F

R/(W)*

[Setting condition]

• When the interrupt selected by ISCR occurs

[Clearing conditions]

• Writing 0 after reading IRQ15 = 1

• When IRQ15 interrupt exception handling is

executed while falling-edge sensing is selected

IRQ14F*

R/(W)*

[Setting condition]

• When the interrupt selected by ISCR occurs

[Clearing conditions]

• Writing 0 after reading IRQ14 = 1

When IRQ14 interrupt exception handling is executed

while falling-edge sensing is selected

13, 12



All 0

R/(W)*

Reserved

These bits are always read as 0. The write value should

always be 0.

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