H8SXSLASH1663R datasheet(181/1504 Pages) RENESAS

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Section 7 Interrupt Controller

Rev. 2.00 Sep. 24, 2008 Page 149 of 1468

REJ09B0412-0200

7.5

Interrupt Exception Handling Vector Table

Table 7.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority.

In the default priority order, a lower vector number corresponds to a higher priority. When

interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The

priority for interrupt sources allocated to the same level in IPR follows the default priority, that is,

they are fixed.

Table 7.2

Interrupt Sources, Vector Address Offsets, and Interrupt Priority

Vector Address Offset*

Classification

Interrupt Source

Vector

Number

Advanced mode,

Middle mode, Maximum

mode

IPR

Priority

DTC

Activation

DMAC

Activation

External pin

NMI

H'001C



UBC

UBC break

interrupt

H'0038



IRQ0

H'0100

IPRA14 to IPRA12



IRQ1

H'0104

IPRA10 to IPRA8



IRQ2

H'0108

IPRA6 to IPRA4



IRQ3

H'010C

IPRA2 to IPRA0



IRQ4

H'0110

IPRB14 to IPRB12



IRQ5

H'0114

IPRB10 to IPRB8



IRQ6

H'0118

IPRB6 to IPRB4



IRQ7

H'011C

IPRB2 to IPRB0



IRQ8

H'0120

IPRC14 to IPRC12



IRQ9

H'0124

IPRC10 to IPRC8



IRQ10

H'0128

IPRC6 to IPRC4



External pin

IRQ11

H'012C

IPRC2 to IPRC0



H'0130



Reserved for

system use

H'0134



LVD*

Voltage-

monitoring

interrupt *(IRQ14)

H'0138

IPRD6 to IPRD4

High



TM32K

32KOVI (IRQ15)

H'013C

IPRD2 to IPRD0

Low



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