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H8SX/1663R データシート(PDF) 280 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 280 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 248 of 1468
REJ09B0412-0200
(2)
16-Bit 3-State Access Space
Figures 9.18 to 9.20 show the bus timing of 16-bit 3-state access space.
When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even
addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be
inserted.
1. n = 0 to 7
2. When RDNn = 0
3. When DKC and EDKC = 0
Notes:
DACK or EDACK
Valid
Invalid
T
1
T
2
T
3
Address
CSn
AS
RD
D15 to D8
D7 to D0
D15 to D8
D7 to D0
LHWR
LLWR
High level
High-Z
B
φ
Bus cycle
Valid
BS
RD/
WR
Read
Write
Figure 9.18 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)



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