H8SXSLASH1663R datasheet(301/1504 Pages) RENESAS

301 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 269 of 1468

REJ09B0412-0200

9.8.5

Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion by the

WAIT

pin can be used in the initial cycle (full access) on the burst ROM interface. See section 9.6.4,

Wait Control. Wait cycles cannot be inserted in a burst cycle.

9.8.6

Read Strobe (

RD) Timing

When the burst ROM space is read by the CPU or EXDMAC cluster transfer, the RDNCR setting

for the corresponding space is invalid.

The read strobe negation timing is the same timing as when RDNn = 0 in the basic bus interface.

9.8.7

Extension of Chip Select (

CS) Assertion Period

In the burst ROM interface, the extension cycles can be inserted in the same way as the basic bus

interface.

For the burst ROM space, the burst access can be enabled only in read access by the CPU or

EXDMAC cluster transfer. In this case, the setting of the corresponding CSXTn bit in CSACR is

ignored and an extension cycle can be inserted only before the full access cycle. Note that no

extension cycle can be inserted before or after the burst access cycles.

In accesses other than read accesses by the CPU and EXDMAC cluster transfer, the burst ROM

space is equivalent to the basic bus interface space. Accordingly, extension cycles can be inserted

before and after the burst access cycles.

H8SX/1663R データシート(PDF) 301 Page - Renesas Technology Corp