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H8SX/1663R データシート(PDF) 318 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 318 Page - Renesas Technology Corp |
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318 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 286 of 1468 REJ09B0412-0200 9.10.8 Controlling Precharge Cycle The number of precharge cycles (Tp) can be selected from one to four clock cycles by bits TPC1 and TPC0 in DRACCR. Set the bit according to the DRAM to be used and the frequency of this LSI so that the number of precharge cycle can be optimal. Figure 9.42 shows an access timing example when two Tp cycles are specified. The setting of bits TPC1 and TPC0 affect the Tp cycle of a refresh cycle. T p1 T p2 T r T c1 T c2 Address bus Row address Column address B φ RAS LUCAS LLCAS WE OE (RD) WE OE (RD) Data bus High High Read Write Data bus BS RD/ WR Figure 9.42 Access Timing Example of Two Precharge Cycles (RAST = 0 and CAST = 0) |
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