H8SXSLASH1663R datasheet(400/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 368 of 1468

REJ09B0412-0200

9.16.2

Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority over that of the bus

master that has taken control of the bus and is currently operating, the bus is not necessarily

transferred immediately. There are specific timings at which each bus master can release the bus.

(1)

CPU

The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or

DMAC, the bus arbiter transfers the bus to the bus master that issued the request. When the CPU

accesses the external space and a bus request is received from the EXDMAC, the external bus

arbiter transfer the bus to the EXDMAC.

The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is

transferred synchronously with the clock.

Note, however, that the bus cannot be transferred in the following cases.

• The word or longword access is performed in some divisions.

• Stack handling is performed in multiple bus cycles.

• Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS

instruction.

(In the block transfer instructions, the bus can be transferred in the write cycle and the

following transfer data read cycle.)

• From the target read to write in the bit manipulation instructions or memory operation

instructions.

(In an instruction that performs no write operation according to the instruction condition, up to

a cycle corresponding the write cycle)

(2)

DTC

The DTC sends the internal bus arbiter a request for the bus when an activation request is

generated. When the DTC accesses an external bus space, the DTC first takes control of the bus

from the internal bus arbiter and then requests a bus to the external bus arbiter.

Once the DTC takes control of the bus, the DTC continues the transfer processing cycles. If a bus

master whose priority is higher than the DTC requests the bus, the DTC transfers the bus to the

higher priority bus master. If the IBCCS bit in BCR2 is set to 1, the DTC transfers the bus to the

CPU.

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