H8SXSLASH1663R datasheet(402/1504 Pages) RENESAS

402 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 370 of 1468

REJ09B0412-0200

• Transfers are continued without bus release when a bus master with priority over the DMAC is

not requesting the bus, the EBCCS bit in BCR2 is cleared to 0, and either the following

conditions are executed.

 While one block of data is being transferred in block transfer mode

 While data is being transferred in burst mode

A transfer other than the above is stopped and the bus is passed when the bus cycle is completed.

However, the EXDMAC takes control of the bus and EXDMAC transfers are continued when

multiple channels in the EXDMAC request the bus while other bus masters are not requesting the

bus.

(5)

External Bus Release

When the

BREQ pin goes low and an external bus release request is issued while the BRLE bit in

BCR1 is set to 1 with the corresponding ICR bit set to 1, a bus request is sent to the bus arbiter.

External bus release can be performed on completion of an external bus cycle.

(6)

Refresh

When area 2 is specified as the DRAM space or SDRAM space with the RFSHE bit in REFCR set

to 1, RTCNT starts to count up. When the RTCOR value matches RTCNT, a bus request is sent to

the bus arbiter.

A refresh cycle is inserted on completion of the external bus cycle. A refresh cycle is not

consecutively inserted. Once a refresh cycle is inserted, the bus is passed to another bus master.

When the bus is passed, if there is no bus request from other bus masters, NOP cycles are inserted.

H8SX/1663R データシート(PDF) 402 Page - Renesas Technology Corp