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H8SX/1663R データシート(PDF) 412 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 412 Page - Renesas Technology Corp

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Section 10 DMA Controller (DMAC)
Rev. 2.00 Sep. 24, 2008 Page 380 of 1468
REJ09B0412-0200
Channel 3:
• DMA source address register_3 (DSAR_3)
• DMA destination address register_3 (DDAR_3)
• DMA offset register_3 (DOFR_3)
• DMA transfer count register_3 (DTCR_3)
• DMA block size register_3 (DBSR_3)
• DMA mode control register_3 (DMDR_3)
• DMA address control register_3 (DACR_3)
• DMA module request select register_3 (DMRSR_3)
10.3.1
DMA Source Address Register (DSAR)
DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR
updates the transfer source address every time data is transferred. When DDAR is specified as the
destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored.
Although DSAR can always be read from by the CPU, it must be read from in longwords and
must not be written to while data for the channel is being transferred.
31
0
R/W
30
0
R/W
29
0
R/W
28
0
R/W
27
0
R/W
24
0
R/W
26
0
R/W
25
0
R/W
Bit
Bit Name
Initial Value
R/W
23
0
R/W
22
0
R/W
21
0
R/W
20
0
R/W
19
0
R/W
16
0
R/W
18
0
R/W
17
0
R/W
Bit
Bit Name
Initial Value
R/W
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
8
0
R/W
10
0
R/W
9
0
R/W
Bit
Bit Name
Initial Value
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Bit Name
Initial Value
R/W



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