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H8SX/1663R データシート(PDF) 463 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 463 Page - Renesas Technology Corp |
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463 / 1504 page  Section 10 DMA Controller (DMAC) Rev. 2.00 Sep. 24, 2008 Page 431 of 1468 REJ09B0412-0200 Address bus DMA word write cycle DMA byte read cycle DMA byte read cycle DMA word read cycle DMA word write cycle DMA word write cycle DMA byte read cycle DMA byte read cycle DMA word read cycle DMA word write cycle B φ RD LLWR LHWR TEND Bus released Bus released Bus released Last transfer cycle 4m + 1 4m + 2 4m + 4 4n + 4 4n + 6 4n 4n +2 4m + 5 4m + 6 4m + 8 m and n are integers. Figure 10.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment) DMA word read cycle DMA byte write cycle DMA word read cycle Address bus DMA byte write cycle DMA byte write cycle DMA word write cycle DMA word read cycle DMA byte write cycle DMA word read cycle DMA word write cycle B φ RD LLWR LHWR TEND Bus released Bus released Bus released Last transfer cycle 4m 4m + 2 4n + 5 4n + 2 4n + 4 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 m and n are integers. Figure 10.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement) |
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