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H8SX/1663R データシート(PDF) 464 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 464 Page - Renesas Technology Corp |
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464 / 1504 page  Section 10 DMA Controller (DMAC) Rev. 2.00 Sep. 24, 2008 Page 432 of 1468 REJ09B0412-0200 (2) Normal Transfer Mode (Burst Mode) In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed. In figure 10.27, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by burst access. DMA read cycle DMA read cycle DMA write cycle Address bus DMA write cycle DMA read cycle DMA write cycle B φ RD LHWR, LLWR TEND Bus released Bus released Last transfer cycle Burst transfer Figure 10.27 Example of Transfer in Normal Transfer Mode by Burst Access |
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