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H8SX/1663R データシート(PDF) 548 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 548 Page - Renesas Technology Corp

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Section 11 EXDMA Controller (EXDMAC)
Rev. 2.00 Sep. 24, 2008 Page 516 of 1468
REJ09B0412-0200
(2)
Single Address Mode (Write in Cycle Steal Mode)
In single address mode, the bus is released after one byte, word, or longword has been transferred
in response to one transfer request. While the bus is released, one or more CPU, DMAC, or DTC
bus cycles are initiated.
Figure 11.35 shows an example of transfer when
ETEND output is enabled, and byte-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
Bus
release
Bus
release
EXDMA write
B
φ
Address bus
Bus
release
Bus
release
Last transfer
cycle
ETEND
EDACK
EXDMA write
EXDMA write
EXDMA write
LLWR
Bus
release
Figure 11.35 Example of Single Address Mode (Byte Write) Transfer



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