H8SXSLASH1663R datasheet(130/1504 Pages) RENESAS

130 / 1504 page

Section 4 Resets

Rev. 2.00 Sep. 24, 2008 Page 98 of 1468

REJ09B0412-0200

4.3

This LSI has the following registers for resets.

• Reset status register (RSTSR)

• Reset control/status register (RSTCSR)

4.3.1

Reset Status Register (RSTSR)

RSTSR indicates a source for generating an internal reset and voltage monitoring interrupt.

Bit

Bit name

Initial value:

R/W:

DPSRSTF

R/(W)*1



R/W



R/W



R/W



R/W

LVDF*2

0*3

R/W*4



0*3

R/W

PORF*2

0*3

R/W*5

Notes:

Only 0 can be written to clear the flag.

Supported only by the H8SX/1668M Group.

Initial value is undefined in the H8SX/1668M Group.

Only 0 can be written to clear the flag in the H8SX/1668M Group.

Only read is possible in the H8SX/1668M Group.

Bit

Bit Name

Initial

Value

R/W

Description

DPSRSTF

R/(W)*

Deep Software Standby Reset Flag

Indicates that deep software standby mode is canceled

by an interrupt source specified with DPSIER or

DPSIEGR and an internal reset is generated.

[Setting condition]

When deep software standby mode is canceled by an

interrupt source.

[Clearing conditions]

• When this bit is read as 1 and then written by 0.

• When a pin reset, power-on reset*2 or voltage-

monitoring reset*

2 is generated.

6 to 3



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

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