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H8SX/1663R データシート(PDF) 134 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 134 Page - Renesas Technology Corp |
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134 / 1504 page ![]() Section 4 Resets Rev. 2.00 Sep. 24, 2008 Page 102 of 1468 REJ09B0412-0200 V V V Vpor *1 External power supply Vcc Vcc Vcc Vcc Vcc RES pin POR signal ("L" is valid) Reset signal ("L" is valid) Pin reset and OR signal for POR PORF Reset state Reset state tPOR*2 tPOR*2 Set Set Notes: For details of the electrical characteristics, see section 30, Electrical Characteristics. 1. V POR shows a level of power-on reset detection level. 2. T POR shows a time for power-on reset. Figure 4.2 Operation of a Power on Reset 4.6 Power Supply Monitoring Reset (H8SX/1668M Group) This is an internal reset generated by the power-supply detection circuit. When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to 1 and the LVDRI bit has been cleared to 0, a voltage-monitoring reset is generated. When Vcc subsequently rises above Vdet, release from the voltage-monitoring reset proceeds after a specified time has elapsed. For details of the voltage-monitoring reset, see section 5, Voltage Detection Circuit (LVD), and section 30, Electrical Characteristics. |
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