H8SXSLASH1663R datasheet(139/1504 Pages) RENESAS

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Section 5 Voltage Detection Circuit (LVD)

Rev. 2.00 Sep. 24, 2008 Page 107 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial Value

R/W

Description

LVDMON

LVD Monitor

This bit monitors the voltage level. This bit is valid

when the LVDE bit is 1 and read as 0 when the

LVDE bit is 0. Writing to this bit is ineffective.

0: Vcc must fall below Vdet.

1: Vcc must rise above Vdet.

3 to 0

—

R/W

Reserved

These bits are always read as 0 and the write

value should always be 0.

5.2.2

Reset Status Register (RSTSR)

RSTSR indicates the source of an internal reset or voltage monitoring interrupt.

Note:

To clear the flag, only 0 should be written to.

DPSRSTF

R/(W)

—

R/W

—

R/W

—

R/W

—

R/W

LVDF

Undefined

R/(W)

—

Undefined

R/W

PORF

Undefined

Bit

Bit name

Initial value:

R/W:

Bit

Bit Name

Initial Value

R/W

Description

DPSRSTF

R/W*

Deep Software Standby Reset Flag

This bit indicates release from deep software

standby mode due to the interrupt source

selected by DPSIER and DPSIEGR, and

generation of an internal reset.

[Setting condition]

Release from deep software standby mode due to

an interrupt source.

[Clearing condition]

•

Writing 0 to the bit after reading it as1.

•

Generation of a pin reset, power on reset, or

voltage monitoring reset.

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