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H8SX/1663R データシート(PDF) 140 Page - Renesas Technology Corp |
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H8SX/1663R データシート(HTML) 140 Page - Renesas Technology Corp |
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140 / 1504 page ![]() Section 5 Voltage Detection Circuit (LVD) Rev. 2.00 Sep. 24, 2008 Page 108 of 1468 REJ09B0412-0200 Bit Bit Name Initial Value R/W Description 6 to 3 — All 0 R/W Reserved These bits are always read as 0 and the write value should always be 0. 2 LVDF Undefined R/(W)* LVD Flag This bit indicates that the voltage detection circuit has detected a low voltage (Vcc at or below Vdet). [Setting condition] Vcc falling to or below Vdet. [Clearing condition] • After Vcc has exceeded Vdet and the specified stabilization period has elapsed, writing 0 to the bit after reading it as 1. • Generation of a pin reset or power-on reset. 1 — Undefined R/W Reserved The write value should always be 0. 0 PORF Undefined R Power-on Reset Flag This bit indicates that a power-on reset has been generated. [Setting condition] Generation of a power-on reset [Clearing condition] Generation of a pin reset Note: * To clear the flag, only 0 should be written to. |
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