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H8SX/1663R データシート(PDF) 224 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 224 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 192 of 1468
REJ09B0412-0200
Bit
Bit Name
Initial
Value
R/W
Description
14
13
12
W32
W31
W30
1
1
1
R/W
R/W
R/W
Area 3 Wait Control 2 to 0
These bits select the number of program wait cycles
when accessing area 3 while bit AST3 in ASTCR is 1.
000: Program wait cycle not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted
11
0
R
Reserved
This is a read-only bit and cannot be modified.
10
9
8
W22
W21
W20
1
1
1
R/W
R/W
R/W
Area 2 Wait Control 2 to 0
These bits select the number of program wait cycles
when accessing area 2 while bit AST2 in ASTCR is 1.
When SDRAM is connected, the CAS latency is
specified. At this time, W22 is ignored. The CAS latency
can be specified even if the wait cycle insertion is
disabled by ASTCR.
Selection of number of program wait cycles:
000: Program wait cycle not inserted
001: 1 program wait cycle inserted
010: 2 program wait cycles inserted
011: 3 program wait cycles inserted
100: 4 program wait cycles inserted
101: 5 program wait cycles inserted
110: 6 program wait cycles inserted
111: 7 program wait cycles inserted
Setting of CAS latency (W22 is ignored.):
00: Setting prohibited
01: SDRAM with a CAS latency of 2 is connected.
10: SDRAM with a CAS latency of 3 is connected.
11: SDRAM with a CAS latency of 4 is connected.



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