H8SXSLASH1663R datasheet(227/1504 Pages) RENESAS

部品番号	H8SX/1663R

部品情報	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 195 of 1468

REJ09B0412-0200

Bus cycle

Data

RDNn = 0

RDNn = 1

(n = 7 to 0)

Figure 9.2 Read Strobe Negation Timing (Example of 3-State Access Space)

9.2.5

CS Assertion Period Control Registers (CSACR)

CSACR selects whether or not the assertion periods of the chip select signals (

CSn) and address

signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O

interface are to be extended. Extending the assertion period of the

CSn and address signals allows

the setup time and hold time of read strobe (

RD) and write strobe (LHWR/LLWR) to be assured

and to make the write data setup time and hold time for the write strobe become flexible.

Bit

Bit Name

Initial Value

R/W

CSXH7

R/W

CSXH6

R/W

CSXH5

R/W

CSXH4

R/W

CSXH3

R/W

CSXH2

R/W

CSXH1

R/W

CSXH0

R/W

Bit

Bit Name

Initial Value

R/W

CSXT7

R/W

CSXT6

R/W

CSXT5

R/W

CSXT4

R/W

CSXT3

R/W

CSXT2

R/W

CSXT1

R/W

CSXT0

R/W

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