データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

H8SX/1663R データシート(PDF) 232 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 232 Page - Renesas Technology Corp

Back Button H8SX/1663R Datasheet HTML 228Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 229Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 230Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 231Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 232Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 233Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 234Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 235Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 236Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 232 / 1504 page
background image
Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 200 of 1468
REJ09B0412-0200
9.2.7
Bus Control Register 1 (BCR1)
BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the
write data buffer function, and enabling/disabling of the
WAIT pin input.
Bit
Bit Name
Initial Value
R/W
15
BRLE
0
R/W
14
BREQOE
0
R/W
13
0
R
12
0
R
11
0
R/W
10
0
R/W
9
WDBE
0
R/W
8
WAITE
0
R/W
Bit
Bit Name
Initial Value
R/W
7
DKC
0
R/W
6
EDKC
0
R/W
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
Bit
Bit Name
Initial Value
R/W
Description
15
BRLE
0
R/W
External Bus Release Enable
Enables/disables external bus release.
0: External bus release disabled
BREQ, BACK, and BREQO pins can be used as
I/O ports
1: External bus release enabled*
For details, see section 13, I/O Ports.
14
BREQOE
0
R/W
BREQO Pin Enable
Controls outputting the bus request signal (
BREQO)
to the external bus master in the external bus
released state when an internal bus master performs
an external address space access.
0:
BREQO output disabled
BREQO pin can be used as I/O port
1:
BREQO output enabled
13, 12
All 0
R
Reserved
These are read-only bits and cannot be modified.
11, 10
All 0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com