H8SXSLASH1663R datasheet(271/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 239 of 1468

REJ09B0412-0200

(6)

Area 5

Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area

5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that

the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME bit in

SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an

external address space. For details, see section 3, MCU Operating Modes.

When area 5 external address space is accessed, the

CS5 signal can be output.

Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O

interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in

SRAMCR. Table 9.12 shows the external interface of area 5.

Table 9.12

Area 5 External Interface

Interface

MPXE5 of MPXCR

BCSEL5 of SRAMCR

Basic bus interface

Byte control SRAM interface

Address/data multiplexed I/O

interface

Setting prohibited

(7)

Area 6

Area 6 includes internal I/O registers. In external extended mode, area 6 other than on-chip I/O

When area 6 external address space is accessed, the

CS6 signal can be output.

Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O

interface can be selected for area 6 by the MPXE6 bit in MPXCR and the BCSEL6 bit in

SRAMCR. Table 9.13 shows the external interface of area 6.

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