H8SXSLASH1663R datasheet(268/1504 Pages) RENESAS

268 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 236 of 1468

REJ09B0412-0200

(5)

Strobe Assert/Negate Timings

The assert and negate timings of the strobe signals can be modified as well as number of access

cycles.

• Read strobe (RD) in the basic bus interface

• Chip select assertion period extension cycles in the basic bus interface

• Data transfer acknowledge (DACK3 to DACK0) output for DMAC single address transfers

• Data transfer acknowledge (EDACK3 to EDACK0) output for EXDMAC single address

transfers

9.5.5

Area and External Bus Interface

(1)

Area 0

Area 0 includes on-chip ROM. All of area 0 is used as external address space in on-chip ROM

disabled extended mode, and the space excluding on-chip ROM is external address space in on-

chip ROM enabled extended mode.

When area 0 external address space is accessed, the

CS0 signal can be output.

Either of the basic bus interface, byte control SRAM interface, or burst ROM interface can be

selected for area 0 by bit BSRM0 in BROMCR and bit BCSEL0 in SRAMCR. Table 9.7 shows

the external interface of area 0.

Table 9.7

Area 0 External Interface

Interface

BSRM0 of BROMCR

BCSEL0 of SRAMCR

Basic bus interface

Byte control SRAM interface

Burst ROM interface

Setting prohibited

H8SX/1663R データシート(PDF) 268 Page - Renesas Technology Corp