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H8SX/1663R データシート(PDF) 109 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 109 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 2.00 Sep. 24, 2008 Page 77 of 1468
REJ09B0412-0200
Note:
A transition to the reset state occurs whenever the
STBY signal goes low.
* A transition to the reset state occurs when the
RES signal goes low in all states
except hardware standby mode. A transition can also be made to the reset state
when the watchdog timer overflows.
Reset state*
Exception-handling
state
Request for exception
handling
End of exception
handling
Program execution
state
Bus-released state
Bus
request
End of bus request
Program stop state
SLEEP instruction
Interrupt
request
Bus request
End of
bus request
RES = high
RES = low
STBY = High,
Figure 2.16 State Transitions



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