H8SXSLASH1663R datasheet(118/1504 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev. 2.00 Sep. 24, 2008 Page 86 of 1468

REJ09B0412-0200

3.3.5

Mode 5

The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-

chip ROM is disabled.

The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas.

Ports D, E, and F function as an address bus, port H functions as a data bus, and parts of ports A

and B function as bus control signals. However, if any area is designated as a 16-bit access space

by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data

bus.

3.3.6

Mode 6

The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-

chip ROM is enabled.

The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas.

Ports D, E, and F function as input ports, but they can be used as an address bus by specifying the

data direction register (DDR) for each port. For details, see section 13, I/O Ports. Port H functions

as a data bus, and parts of ports A and B function as bus control signals. However, if any area is

designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits,

and ports H and I function as a data bus.

3.3.7

Mode 7

The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-

chip ROM is enabled.

All I/O ports can be used as general input/output ports. The external address space cannot be

accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1

enables the external address space. After the external address space is enabled, ports D, E, and F

can be used as an address output bus and ports H and I as a data bus by specifying the data

direction register (DDR) for each port. When the external address space is not in use, ports J and

K can be used by setting the PCJKE bit in the port function control register D (PFCRD) to 1. For

details, see section 13, I/O Ports.

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