H8SXSLASH1663R datasheet(153/1504 Pages) RENESAS

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Section 6 Exception Handling

Rev. 2.00 Sep. 24, 2008 Page 121 of 1468

REJ09B0412-0200

Bus Cycle

Type

Bus Master

Description

Address Error

Accesses word data from even addresses

No (normal)

Accesses word data from odd addresses

No (normal)

Accesses external memory space in single-chip

mode

Occurs

Accesses to access prohibited area*

Occurs

Accesses external memory space

No (normal)

Data read/write EXDMAC

Accesses spaces other than external memory

space

Occurs

Address access space is the external memory

space for single address transfer

No (normal)

Single address

transfer

DMAC or

EXDMAC

Address access space is not the external memory

space for single address transfer

Occurs

Notes: 1. For on-chip peripheral module space, see section 9, Bus Controller (BSC).

2. For the access prohibited area, refer to figure 3.1 in section 3.4, Address Map.

6.5.2

Address Error Exception Handling

When an address error occurs, address error exception handling starts after the bus cycle causing

the address error ends and current instruction execution completes. The address error exception

handling is as follows:

1. The contents of PC, CCR, and EXR are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. An exception handling vector table address corresponding to the address error is generated, the

start address of the exception service routine is loaded from the vector table to PC, and

program execution starts from that address.

Even though an address error occurs during a transition to an address error exception handling, the

address error is not accepted. This prevents an address error from occurring due to stacking for

exception handling, thereby preventing infinitive stacking.

If the SP contents are not a multiple of 2 when an address error exception handling occurs, the

stacked values (PC, CCR, and EXR) are undefined.

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