データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

H8SX/1663R データシート(PDF) 155 Page - Renesas Technology Corp

部品番号 H8SX/1663R
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R データシート(HTML) 155 Page - Renesas Technology Corp

Back Button H8SX/1663R Datasheet HTML 151Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 152Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 153Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 154Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 155Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 156Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 157Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 158Page - Renesas Technology Corp H8SX/1663R Datasheet HTML 159Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 155 / 1504 page
background image
Section 6 Exception Handling
Rev. 2.00 Sep. 24, 2008 Page 123 of 1468
REJ09B0412-0200
6.6
Interrupts
6.6.1
Interrupt Sources
Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 6.7.
Table 6.7
Interrupt Sources
Type
Source
Number of Sources
NMI
NMI pin (external input)
1
UBC break
interrupt
UBC break controller (UBC)
1
IRQ0 to IRQ11
Pins
IRQ0 to IRQ11 (external input)
12
Voltage-detection
circuit*
Voltage-detection circuit (LVD)
*
1
32K timer (TM32K)
1
DMA controller (DMAC)
8
EXDMA controller (EXDMAC)
8
Watchdog timer (WDT)
1
A/D converter
2
16-bit timer pulse unit (TPU)
52
8-bit timer (TMR)
16
Serial communications interface (SCI)
24
I
2C bus interface 2 (IIC2)
2
On-chip peripheral
module
USB function module (USB)
5
Note:
*
Supported only by the H8SX/1668M Group.
Different vector numbers and vector table offsets are assigned to different interrupt sources. For
vector number and vector table offset, refer to table 7.2, Interrupt Sources, Vector Address
Offsets, and Interrupt Priority in section 7, Interrupt Controller.
6.6.2
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiple-interrupt control. The source to start interrupt exception handling and the vector address
differ depending on the product. For details, refer to section 7, Interrupt Controller.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com