H8SXSLASH1663R datasheet(151/1504 Pages) RENESAS

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Section 6 Exception Handling

Rev. 2.00 Sep. 24, 2008 Page 119 of 1468

REJ09B0412-0200

6.4

Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control

mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit

must be cleared. For details on interrupt control modes, see section 7, Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on

completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table

6.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is

canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit

saved on the stack retains its value of 1, and when control is returned from the trace exception

handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not

carried out after execution of the RTE instruction.

Interrupts are accepted even within the trace exception handling routine.

Table 6.4

Status of CCR and EXR after Trace Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0

Trace exception handling cannot be used.



[Legend]

Set to 1

Cleared to 0

:

Retains the previous value.

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